12 wanggongzhen1983



TA的排名 7w+

VIVT VIPT PIPT Properties of Each Caching Strategy

Properties of Each Caching Strategy Properties of Each Caching Strategy Why use VIPT caches if they have this inherent page colouring restriction? The simplest (and perhaps fastest) cache...

2019-10-30 19:04:38


将kernel inline改为uninline 修改代码为include/linux/compiler-gcc.h #if 0 //wgz remove inline#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \ !defined(CONFIG_OPTIMIZE_INLINING) || (__...

2019-09-02 10:40:22

DMA Buffer Sharing API Guide

DMA Buffer Sharing API Guide ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Sumit Semwal <sumit dot semwal at linaro dot org>...

2019-08-20 13:27:23

E2.9 Wake-up Signaling

The wake-up signals are used to indicate that there is activity associated with the interface. These are: • AWAKEUP. • ACWAKEUP. The Wakeup_Signals property is used to indicate whether a comp...

2019-08-18 08:24:07

E2.8 QoS Accept signaling

AXI4 introduced two interface signals to indicate the QoS value of a transaction. AMBA 5 introduced two additional interface signals that enable a slave to indicate the minimum QoS value of transactio...

2019-08-17 18:14:50

A8.1 QoS signaling

A8.1.1 QoS interface signalsThe AXI4 signal set is extended to support two 4-bit QoS identifiers: AWQOS A 4-bit QoS identifier, sent on the write address channel for each write transaction. AR...

2019-08-17 17:49:08

E2.1 Atomic transactions

Previous generations of AMBA have included Exclusive accesses. See Exclusive accesses on page A7-98. AMBA 5 introduces Atomic transactions, which perform more than just a single access, and have some ...

2019-08-17 13:36:27

D4.10 Handling overlapping write transactions

This section describes the expected behavior when two masters attempt stores to the same cache line in a Shareable region of memory at approximately the same time. When this happens, it is the respons...

2019-07-06 19:12:36

D4.4 State change descriptions

For each transaction, the starting state for the transaction and the three possible end state groups are given. The three possible end state groups are: • The expected end states, which are ...

2019-07-06 18:32:03

D4.3 State changes on different transactions

The state changes that can be associated with a transaction are determined by: • The transaction type. • The read response for transactions that are issued on the AR channel. • Whether the ma...

2019-07-06 18:02:38

D4.2 About snoop filtering

Snoop filtering tracks the cache lines that are allocated in a master’s cache. To support an external snoop filter, a cached master must be able to broadcast cache lines that are allocated and cacheli...

2019-07-06 15:38:07

D4.1 About an initiating master

The internal action requires: • For a load, the master must get the data from either: — A valid copy of the appropriate cache line. — A transaction that returns valid read data. • For a st...

2019-07-06 15:30:10

D4.9 Evict transactions

An Evict transaction indicates that a cache line has been evicted from a master’s local cache. There is no data transfer associated with an Evict transaction. An Evict transaction must be used only in...

2019-07-06 10:19:30

Chapter B1 The AArch64 Application Level Programmers’ Model

B1.1 About the Application level programmers’ modelEL0 corresponds to the lowest privilege level and is often described as unprivileged.• Permits the operating system to allocate system resources ...

2019-07-06 09:54:14

B2.1 About the Arm memory model

总览 The Arm architecture is a weakly ordered memory architecture that permits the observation and completion of memory accesses in a different order from the program order. The following sections of t...

2019-07-06 09:54:07

armv8笔记--Chapter A1 Introduction to the ARMv8 Architecture

A load/store architecture, where data-processing operations only operate on register contents, not directly onmemory contents.只能操作寄存器,不能直接操作内存Simple addressing modes, with all load/store addresse...

2019-07-06 09:54:01

B2.2 Atomicity in the Arm architecture

B2.1 About the Arm memory modelB2.2.1 Requirements for single-copy atomicitysingle-copy atomicity • A read that is generated by a load instruction that loads a single general-purpose register and...

2019-07-06 09:53:51

D4.7 Make transactions

D4.7.1 MakeUniqueA MakeUnique transaction is used in a region of memory that is Shareable with other masters. The MakeUnique transaction ensures that: • The cache line can be held in a Unique sta...

2019-07-06 09:49:53

D4.5 Read transactions

D4.5.1 ReadNoSnoop ReadNoSnoop is a read transaction that is used in a region of memory that is not Shareable with other masters. The transaction response requirements are: • The IsShared resp...

2019-07-06 07:51:30

D4.6 Clean transactions

This section defines the state changes associated with the Clean transaction group that are issued on the AR channel. clean操作都是在AR channel上发出的。 D4.6.1 CleanUniqueA CleanUnique transaction is us...

2019-07-06 06:44:10


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