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原创海思移植opencv直接进行图像处理

前言:几年前基础海思,当时做了个火焰探测的项目,变使用了opencv,苦于网上没有资料,都是编译这块的资料;后先后把Opencv移植到hi35183v200/hi3516dv100/hi3516dv300/hi359av100/rv1126/寒武纪目前到了在做自己的Sigmastar SSC33X 38板开始预售,希望有个好彩头Copy海思移植opencv步骤交叉编译opencv,网上资料很多,再次不多说; 1.版本选择,海思官方SDK已经说明,很多的图像接口都是参...

2022-02-19 10:49:48 3688 3

原创公网服务器绑定域名

2022-02-17 20:58:34 563

原创 RGB888和RGB565互相转换

一.RGB888->RGB565方法只要提取相应单色高位即可(R5 G6 B5)，但会导致低位的缺失，影响精度，而且无法恢复。二.RGB565->RGB888方法只要补充相应单色低位即可(R3 G2 B3)。RGB888用unsigned int 32位字节存储 0 0 0 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0RGB565用unsigned short

2022-02-17 20:40:13 5792 1

原创瑞芯微rv1126超频笔记

Print Encode Frame Rateenable print fps logecho 0x100 > /sys/module/rk_vcodec/parameters/mpp_dev_debugdisable print fps logecho 0 > /sys/module/rk_vcodec/parameters/mpp_dev_debugCPU温度:Print CPU Thermalcat /sys/class/thermal/thermal_zone0/tem

2022-02-17 20:36:56 6109 3

原创 gitLab数据备份和迁移

自建的Gitlab服务器常常会因为使用时间的增长，其空间容量等硬件需求都需要升级，或者迁移至更高配置的服务器上。备份、迁移、恢复、升级过程如下一、gitlab备份备份前gitlab的项目如图所示1.1 修改仓库存储位置gitlab通过rpm包安装后，默认存储位置在/var/opt/gitlab/git-data/repositories，通常需要更改此路径到单独的一个分区来存储仓库的数据。例如我这里把数据存放到/data/gitlab目录下创建/data/gitlab目...

2022-02-17 20:31:55 22154 1

FS6818芯片手册破解版可复制

r To access RTC Time Count Read Register (RTCCNTREAD) and RTC Time Count Setting Register (RTCCNTWRITE), the RTCCTRL.RTCCNTWRITEENB bit is set to "1" before accessing these register. When the CPU completes to access these register, the CPU should set the RTCCTRL.RTCCNTWRITEENB bit to "0" to protect the content of RTC counter from unknown problem in abnormal state. The RTCCNTWRITEENB bit determines the reflection of the RCCNTWRITE register value to the RTC counter. 12.4.4 Interrupt Pending Register Only the "READ" function is available for the RTCINTPND register of the S5P6818, but the current pending status can be read. Since the RTCINTPND register only has a "READ" function, the Pending Clear function is controlled by the RTCINTENB register. The Interrupt Pending status is cleared by disabling the relevant interrupt. Therefore, if the corresponding bit of the RTCINTENB register is set as "1", the relevant interrupt is enabled. If the corresponding bit is set as "0", the interrupt is disabled and the pending bit is also cleared. 12.4.5 Power Manager Reset Time Control RTC controls the time when nPWRMANRST (Power Manager Reset) releases from CorePOR. Refer to RTCCORERSTIMESEL Register for setting the time when nPWRMANRST releases

2018-05-22

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原创 海思移植opencv直接进行图像处理

原创 公网服务器绑定域名