jihengzhang的专栏

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DVI 1.0 encode and decode source code, write with verilog, with simulation project, synplify project and all soure code. They're have been running on xilinx spartan3A FPGA. Can be used in real project directly. Use 3 DCM and about 2000 slices. Also including version_list file. file_list: core\ vssver.scc chnlbond.v dcminit.v decode.v DRAM16XN.v dvi_decoder.v dvi_encoder.v dvi_ip.v encode.v patten_gen.v phsaligner.v resync_1024fifo.v serdes_4b_10to1_fifo.v sync_monitor.v tmds_1c_1to10.v watch_dog.v resync_part_new.vhd