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原创【汇编语言实验九】

在屏幕中间显示‘welcome to masm!

2024-04-17 13:46:23 66

module led_test(input rst,input clk,output reg [3:0]led);reg [31:0] timer;always @(posedge clk or negedge rst)begin if (!rst) timer <=32'd0; else if (timer == 32'd299_999_999) timer <=32'd0; else timer <= timer +1;endalways @(

2020-09-21 15:20:03 160

原创 Exams/review2015 fsm

https://hdlbits.01xz.net/wiki/Exams/review2015_fsmmodule top_module ( input clk, input reset, // Synchronous reset input data, output shift_ena, output counting, input done_counting, output done, input ack ); par

2020-08-26 16:24:37 558

原创 Exams/review2015 fsmshift

https://hdlbits.01xz.net/wiki/Exams/review2015_fsmshiftmodule top_module ( input clk, input reset, // Synchronous reset output shift_ena); parameter S0=0,S1=1,S2=2,S3=3,S4=4,S5=5; reg [2:0] cs,ns; always@(*) begin

2020-08-26 15:12:07 382

原创 Exams/review2015 fsmseq

https://hdlbits.01xz.net/wiki/Exams/review2015_fsmseqmodule top_module ( input clk, input reset, // Synchronous reset input data, output start_shifting); parameter S0=0,S1=1,S2=2,S3=3,S4=4; reg [2:0] cs,ns; always @(*)

2020-08-26 14:59:26 777

原创 Exams/review2015 shiftcount

Exams/review2015 shiftcountmodule top_module ( input clk, input shift_ena, input count_ena, input data, output [3:0] q); always @(posedge clk) begin case ({shift_ena,count_ena}) 2'b00:q<=q;

2020-08-26 14:41:22 306

原创 hdlbits_Exams/2012_q2fsm

https://hdlbits.01xz.net/wiki/Exams/2012_q2fsmmodule top_module ( input clk, input reset, // Synchronous active-high reset input w, output z); parameter A=0,B=1,C=2,D=3,E=4,F=5; reg [2:0]state,next; always @(*) begin

2020-06-10 14:21:56 284

原创 hdlbits_Exams/m2014_q6b

https://hdlbits.01xz.net/wiki/Exams/m2014_q6bmodule top_module ( input [3:1] y, input w, output Y2); reg [3:1]d; parameter A=0,B=1,C=2,D=3,E=4,F=5; always@(*) begin case(y) A:d = w?A:B;

2020-06-08 20:48:36 868

原创 hdlbits_Exams/2014_q3c

https://hdlbits.01xz.net/wiki/Exams/2014_q3cmodule top_module ( input clk, input [2:0] y, input x, output Y0, output z); parameter S0=0,S1=1,S2=2,S3=3,S4=4; reg [2:0]Y1; always@(*) begin case(y)

2020-06-05 20:14:17 860 1

原创 hdlbits_Exams/2014_q3bfsm

https://hdlbits.01xz.net/wiki/Exams/2014_q3bfsmmodule top_module ( input clk, input reset, // Synchronous reset input x, output z); parameter S0=0,S1=1,S2=2,S3=3,S4=4; reg [2:0] cs,ns; always@(*) begin

2020-06-05 19:37:47 231

原创 hdlbits_Exams/2014_q3fsm

https://hdlbits.01xz.net/wiki/Exams/2014_q3fsmerror info:module top_module ( input clk, input reset, // Synchronous reset input s, input w, output z); parameter A=0,B=1; reg state,next; reg[2:0]d; parameter

2020-06-05 19:32:22 543

原创 hdlbits_Exams/ece241_2014_q5b

https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q5b有errormodule top_module ( input clk, input areset, input x, output z); parameter A=0,B=1; reg state, next; always @(*) begin case(state)

2020-06-04 16:59:56 1111

原创 hdlbits_ece241_2013_q8

https://hdlbits.01xz.net/wiki/Exams/ece241_2013_q8module top_module ( input clk, input aresetn, // Asynchronous active-low reset input x, output z ); parameter idle=0,S1=1,S2=2; reg [1:0]state,next; always

2020-06-02 17:20:28 289

原创 hdlbits_Fsm_hdlc

https://hdlbits.01xz.net/wiki/Fsm_hdlc有errormodule top_module( input clk, input reset, // Synchronous reset input in, output disc, output flag, output err); reg [7:0]d; always @(posedge clk) begin

2020-05-31 19:41:29 369 2

原创 Fsm_serialdata_hdlbits

https://hdlbits.01xz.net/wiki/Fsm_serialdata看图发现先进的是bit0module top_module( input clk, input in, input reset, // Synchronous reset output [7:0] out_byte, output done); // reg [9:0] d; // Use FSM from Fsm_serial paramete

2020-05-29 20:56:57 435

原创 hdlbits_Exams/review2015_shiftcount

https://hdlbits.01xz.net/wiki/Exams/review2015_shiftcountmodule top_module ( input clk, input shift_ena, input count_ena, input data, output [3:0] q); always @(posedge clk) begin if (shift_ena) q&

2020-05-27 19:23:58 276

原创 hdlbits_Exams/review2015_fsmseq

https://hdlbits.01xz.net/wiki/Exams/review2015_fsmseq用LFSR 写更简单一些module top_module ( input clk, input reset, // Synchronous reset input data, output start_shifting); reg [3:0] d; always @(posedge clk) begin

2020-05-27 19:19:04 401 1

原创 RAM_verilog_code

/* * Random Access Memory (RAM) with * 1 read port and 1 write port */module ram (clk_write, address_write, data_write, write_enable, clk_read, address_read, data_read); parameter D_WIDTH = 16; parameter A_WIDTH = 4; parameter A_MAX = 16;

2020-05-26 17:22:29 354

原创 Exams/review2015 count1k_hdbits

https://hdlbits.01xz.net/wiki/Exams/review2015_count1kBuild a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0.module top_module ( input clk, input reset

2020-05-25 19:45:24 752

原创 hdlbits_Fsm_serial

module top_module( input clk, input in, input reset, // Synchronous reset output done); parameter stop = 0,b0=1,b1=2,b2=3,b3=4,b4=5,b5=6,b6=7,b7=8,stop_ok=9,stop_notok=10,start = 11; //parameter idle = 0,start = 1,b0=2,b1=3,b2,=4,

2020-05-25 16:46:32 399

原创 hdlbits_Fsm_ps2data

mark: 还有errormodule top_module( input clk, input [7:0] in, input reset, // Synchronous reset output [23:0] out_bytes, output done); // reg [7:0]b0,b1,b2,b3; // FSM from fsm_ps2 reg [1:0]state,next; parameter S0=0,S

2020-05-21 13:44:37 432

原创 hdlbits_Fsm_onehot

module top_module( input in, input [9:0] state, output [9:0] next_state, output out1, output out2); parameter S0 = 10'h1,S1 =10'h2,S2=10'h4,S3=10'h8,S4=10'h10,S5=10'h20,S6=10'h40,S7=10'h80,S8=10'h100,S9=10'h200; always...

2020-05-20 15:37:15 346 1

原创 hdlbits_Lemmings3

有errormodule top_module( input clk, input areset, // Freshly brainwashed Lemmings walk left. input bump_left, input bump_right, input ground, input dig, output walk_left, output walk_right, output aaah, output di

2020-05-20 12:19:09 141

原创 hdlbits_tff

module top_module (); reg clk; reg reset,t; reg q; always #10 clk=~clk; always #20 t=~t; initial begin clk = 0; reset = 0; t=0; #30 reset=1; #10 reset=0;

2020-05-19 16:44:17 106

原创 hdlbits_tb2

module top_module(); reg clk,in,out; reg [2:0] s; always #5 clk = ~clk; initial begin clk = 0; in = 0; s = 3'h2; #10 s=3'h6; #10 s=3'h2;in=1; #10 in = 0;s=3'h7;

2020-05-19 15:38:15 140

原创 hdlbits_Fsm_ps2

module top_module( input clk, input [7:0] in, input reset, // Synchronous reset output done); // parameter S0 =0,S1=1,S2=2,S3=3; reg [1:0] state , next; // State transition logic (combinational) always @(*) begi

2020-05-19 14:10:51 511 1

原创 hdlbits_Lemmings2

module top_module( input clk, input areset, // Freshly brainwashed Lemmings walk left. input bump_left, input bump_right, input ground, output walk_left, output walk_right, output aaah ); parameter WL=0,WR=1,AH_L=2

2020-05-19 11:59:58 257

原创 Lemmings1_hdlbits

module top_module( input clk, input areset, // Freshly brainwashed Lemmings walk left. input bump_left, input bump_right, output walk_left, output walk_right); // // parameter LEFT=0, RIGHT=1, ... reg state, next_state

2020-05-19 11:41:44 155

原创 Fsm3s_hdlbits

module top_module( input clk, input in, input reset, output out); // parameter A=0,B=1,C=2,D=3; reg [1:0]state,next; // State transition logic always @(*) begin case (state) A: next

2020-05-18 22:15:56 232

原创 Fsm3_hdlbits

module top_module( input clk, input in, input areset, output out); // parameter A=0,B=1,C=2,D=3; reg [1:0]state,next; // State transition logic always @(*) begin case (state) A: nex

2020-05-18 22:11:55 261

原创 Fsm3onehot_hdlbits

module top_module( input in, input [3:0] state, output [3:0] next_state, output out); // parameter A=0, B=1, C=2, D=3; // State transition logic: Derive an equation for each state flip-flop. assign next_state[A] = state[A]&amp

2020-05-18 21:56:01 764

原创 Fsm3comb_hdlbits

module top_module( input in, input [1:0] state, output [1:0] next_state, output out); // parameter A=0, B=1, C=2, D=3; //reg state, next; // State transition logic: next_state = f(state, in) always @ (*) begin

2020-05-18 16:37:19 603

原创 Fsm2s_hdlbits

module top_module( input clk, input reset, // Synchronous reset to OFF input j, input k, output out); // parameter OFF=0, ON=1; reg state, next_state; always @(*) begin // State transition logic case

2020-05-18 14:41:23 157

原创 Fsm2_hdlbits

module top_module( input clk, input areset, // Asynchronous reset to OFF input j, input k, output out); // parameter OFF=0, ON=1; reg state, next_state; always @(*) begin // State transition logic cas

2020-05-18 14:09:41 197

原创 Fsm1_hdlbits

状态机学习link：https://wenku.baidu.com/view/9e44f7650066f5335a8121e3.htmlmodule top_module( input clk, input areset, // Asynchronous reset to state B input in, output out);// parameter A=0, B=1; reg state, next_state; alway

2020-05-17 23:34:38 576

原创 Rule110_hdlbits

没有化简module top_module( input clk, input load, input [511:0] data, output [511:0] q); reg [511:0 ]q_l, q_r; assign q_l = {1'b0, q[511:1]}; assign q_r = {q[510:0] , 1'b0}; always @ (posedge clk) begin if

2020-05-15 18:32:34 750 1

原创 Rule90_hdlbits

module top_module( input clk, input load, input [511:0] data, output [511:0] q ); always @ (posedge clk) begin if (load) q <= data; else begin

2020-05-15 16:47:05 1024

原创 Exams/2014 q4b_hdlbits

module top_module ( input [3:0] SW, input [3:0] KEY, output [3:0] LEDR); // reg q1,q2,q3,q4; MUXDFF n4( .clk(KEY[0]), .ain(KEY[3]), .bin(LEDR[3]), .cin(SW[3]), .sel1(KEY[1]), .sel2(KEY[2]

2020-05-15 15:21:26 618

原创 Exams/m2014 q4k_hdlbits

module top_module ( input clk, input resetn, // synchronous reset input in, output out); reg [3:1] q; always @ (posedge clk) begin if (~resetn) {q,out} <= 4'b0; else

2020-05-15 11:28:24 950 1

原创 Lfsr32_hdlbits

module top_module( input clk, input reset, // Active-high synchronous reset to 32'h1 output [31:0] q); reg [31:0] q_next; always @ (*) begin q_next = {q[0], q[31:1]}; q_next[31] = q[0] ^ 1'b0;

2020-05-15 11:14:47 910

空空如也

python 抓的UDP数据与实际不符

用wireshark可以抓到UDP数据包，但是用python socket抓不到数据。